Method of fabricating integrated circuits

ABSTRACT

A method of fabricating integrated circuits is provided that allows new integrated circuits to be fabricated with reduced die areas and reduced power consumptions relative to old integrated circuits. The new circuits are interchangeable with the old integrated circuits, because the delay times for the data pathways through the new circuits are the same as the delay times for the data pathways through the old circuits. A family of new circuits, each of which is compatible with a corresponding one of a series of old circuits, can be fabricated using a common circuit layout. Each new circuit is associated with a parameter value that governs the delay time of a component in a data pathway through the circuit and ensures that the new circuit is compatible with the corresponding old circuit.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional application Ser.No. 60/014,799, filed Apr. 3, 1996.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor integrated circuit fabricationtechniques, and more particularly, to methods for fabricating integratedcircuits that are interchangeable with existing integrated circuits, butwhich have reduced die areas.

The fabrication processes used to manufacture integrated circuits arecontinually improving. Typical advances make it possible to createthinner layers of oxides and to improve doping profiles. Perhaps mostimportantly, newer processes make it possible to reduce the lateraldimensions of structures on the integrated circuit. For example,metal-oxide-semiconductor (MOS) transistors can be fabricated withshorter gate lengths. Reducing the dimensions of the structures on acircuit typically improves the switching speed of the active circuitcomponents and allows the circuit to be fabricated with a smaller diearea. The faster switching speed and smaller die area improve the powerconsumption of the circuit and make the circuit more economical tomanufacture.

Although it may sometimes be acceptable to form a new circuit byuniformly reducing the dimensions of the structures of an old circuitlayout, difficulties can arise if the new circuit no longer conforms tothe performance standards of the old circuit. For example, scaling downcircuitry uniformly may decrease the propagation delays associated withcertain signal pathways more than desired. Such unexpectedly shortpropagation delays could cause compatibility problems between the newcircuit and old systems designed to accommodate older, slower circuits.

It is therefore an object of the present invention to provide a methodfor fabricating integrated circuits using improved fabricationprocesses.

It is a further object of the present invention to provide a method forfabricating integrated circuits that allows a circuit design for an oldcircuit to be implemented using a new fabrication process to produce anew circuit that has a reduced die area relative to the old circuit, yetwhich is compatible with the performance standards of the old circuit.

It is also an object of the present invention to provide an integratedcircuit fabrication method in which a common circuit layout is used tofabricate a family of new circuits each of which is compatible with acorresponding one of a series of old circuits and which has a reduceddie area relative to the corresponding old circuit.

SUMMARY OF THE INVENTION

These and other objects of the invention are accomplished in accordancewith the principles of the present invention by providing a method forfabricating integrated circuits in which new circuit fabricationprocesses are used to produce new circuits that are interchangeable withold circuits using the same circuit design. The new circuits havereduced die areas relative to the old circuits, which make them moreeconomical to manufacture and reduces power consumption.

In order to ensure that the circuits implemented using the new processare interchangeable with versions of the circuit design fabricated withold processes, the die areas of the new circuits are reduced withoutchanging the delay times associated with the data pathways through theold circuits.

One way in which an old circuit can be reduced in size withoutsignificantly changing the performance characteristics of the circuit isto specifically identify those portions of the old circuit that can bereduced in size without affecting the delay times associated withpassing data through the circuit. For example, it may be possible toreduce the area allocated for the testing circuitry and bonding pads onan old circuit without changing the delay times associated with thelogic components on the circuit used to process data. Components thathave been identified as not affecting the delay time of the datapathways through the circuit are reduced in size as much as permitted bythe new process during fabrication on the new circuit.

The die area of an old circuit can also be reduced by shrinking thedimensions of all of the circuitry on the integrated circuit to thegreatest extent permitted by the new process with the exception of arelatively small number of structures in the components in the datapathways of the circuit. Because most circuitry on the new circuit isreduced in size using the new process, the new circuit is smaller thanthe old circuit. However, shrinking the dimensions of all of thecircuitry reduces the delay times associated with certain data pathwaysthrough the circuit. To ensure that the new circuit is compatible withthe old circuit, the delay times of the components containing thestructures are intentionally increased. These intentionally slowercomponents of the new circuit ensure that the data pathways of the newcircuit have total delay times that are equal to those of the oldcircuit. The economies associated with smaller die areas are thereforeachieved while maintaining compatibility with popular older circuits.

A family of new circuits can be fabricated based on a common circuitlayout. Each circuit in the family of new circuits is compatible withone of a series of old circuits that share a common circuit design. Eachnew circuit is associated with at least one parameter value. Theparameter values associated with each circuit govern the size ofstructures in certain circuit components that govern the delay timesassociated with those components.

Further features of the invention, its nature and various advantageswill be more apparent from the accompanying drawings and the followingdetailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an illustrative integrated circuit designimplemented using successively newer fabrication processes.

FIG. 2 is a circuit diagram of the integrated circuit design of FIG. 1implemented using various fabrication processes. The new circuits on theright side of FIG. 2 are interchangeable with corresponding old circuitson the left side of FIG. 2.

FIG. 3 is a flow chart of an illustrative method for fabricatingintegrated circuits in accordance with the present invention.

FIG. 4 is a circuit diagram of a complementary metal-oxide-semiconductor(CMOS) circuit design that can be used to fabricate integrated circuitsusing the method of FIG. 3.

FIG. 5 is a table showing the delay of each of the components of theCMOS circuit design of FIG. 4 for two old circuits and two correspondingnew circuits.

FIG. 6 is a diagram showing a group of old circuits and a family ofcorresponding new circuits fabricated using a common circuit layout.

FIG. 7 is a flow chart of the steps involved in fabricating a family ofnew circuits using a common circuit layout.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An illustrative integrated circuit design implemented using variousfabrication processes is shown in FIG. 1. Integrated circuit 10 has beenfabricated using process 1. Integrated circuit 10 has data inputs 12 and14 and data outputs 16 and 18. Data flows from input 12 to output 16 vialogic circuit components 20 and 22. Logic components 24, 26, 28, and 30perform logic functions on data supplied to input 14 and provide acorresponding data output signal at output 18. Each logic component hasan associated propagation delay. Logic components 24, 26, and 30 eachhave a delay of 10 ns. Logic component 28 has a delay of 15 ns. Datathat passes from data input 14 to data output 18 via components 24, 26,and 28 experiences a total delay of 35 ns.

In addition to logic components, integrated circuit 10 has test circuitsand bonding pads 32, which typically consume approximately half of thedie area of integrated circuit 10. The total die area of integratedcircuit 10 is 100 mm².

When an integrated circuit design is transferred from an old process toa new process, it is generally possible to leave the functionality ofthe circuit undisturbed. For example, the circuit design used tofabricate integrated circuit 10 with process 1 can be used to fabricatedintegrated circuit 34 with process 2. Because the same circuit design isused for both integrated circuits 10 and 34, integrated circuit 34performs the same logic functions as integrated circuit 10. Data inputs36 and 38 of integrated circuit 34 receive data, which is processed bylogic components 40, 42, 44, 46, 48, and 50. Data output signals areprovided at data outputs 52 and 54. Integrated circuit 34 also has testcircuits and pads 56, which perform the same functions as test circuitsand pads 32 of integrated circuit 10.

Although integrated circuit 34 performs the same logic functions asintegrated circuit 10, using fabrication process 2, which is a newer andmore advanced process than process 1, results in a smaller die area anda shorter delay time along the pathways between data inputs and outputs.For example, integrated circuit 34 has a total die area of 90 mm²,rather than 100 mm² for integrated circuit 10. The total delay time forthe data pathway between data input 38 and data output 54 is 24 nscompared with a total delay time of 35 ns for the data pathway betweendata input 14 and data output 18 of integrated circuit 10. Circuitsfabricated with newer processes also exhibit reduced power consumptionrelative to older circuits.

Similar performance improvements are achieved each time the circuitdesign is implemented in a newer process. As shown in FIG. 1, when thecircuit design of integrated circuits 10 and 34 is implemented usingprocess N, the die area of integrated circuit 58 is 70 mm² and the totaldelay time is 18 ns.

The smaller die area of newer integrated circuits is partly the resultof a reduction in the size of testing circuits and bonding pads. Forexample, the smaller die area of integrated circuit 34 compared withintegrated circuit 10 is due in part to a reduction in the size oftesting circuits and pads 56 compared with the size of testing circuitsand pads 32. Improvements in process 2 over process 1 allow thetransistors and other components of the testing circuitry to befabricated in a smaller area. In addition, improvements in process 2 andthe related processes used for forming bonding pad connections allow thesize of the bonding pads to be reduced.

Because test circuits and pads 56 are not used for data functions,reducing the size of test circuits and pads 56 by using process 2 ratherthan process 1 does not affect the delay times associated with the datapathways through circuit 34. However, when the portions of an olderintegrated circuit that are used to perform logic functions areimplemented using a new process, the resulting new circuit willgenerally no longer be compatible with systems designed for use with theolder circuit. When the logic components along the data pathways of thecircuit are fabricated using the new process, the delay times associatedwith the components are reduced.

Specifically, transistors fabricated with the new process have shortergate lengths, which causes them to switch more rapidly. The delay timesof the data pathways in the new circuit will therefore be shorter thanthose of the old circuit. If a system is designed to use a circuit withthe longer data pathway delay times of the old circuit, the new circuitwill not be compatible with the old circuit. Although such a new circuitmay be less expensive than the older circuit because of its reduced diearea, many users of the old circuit will not be able to use the newcircuit in their systems.

Despite the compatibility problems associated with the conventionalapproach, circuit designs are still transferred from older processes tonewer processes to take advantage of the smaller die areas and fasterperformance available with newer fabrication processes. A typicalmigration path is shown in FIG. 1, in which a circuit design issuccessively implemented using process 1, process 2, . . . , and processN. Each fabrication process is more advanced than the previous process.Accordingly, both the die area and the data path delay times are reducedbetween each successive circuit.

The conventional approach for developing successive versions of a commonintegrated circuit design is also shown on the left side of FIG. 2.Process 1 is the oldest, least advanced process and process N is thenewest, most advanced process. Integrated circuits 60, 62, 64, 66, 68,and 70 share a common circuit design. Initially, a circuit design isimplemented using process 1 to produce integrated circuit 60. Whenprocess 2 becomes available, the circuit design of circuit 60 isimplemented using process 2 to produce integrated circuit 62. Whenprocess 3 becomes available, the circuit design of circuit 62 isimplemented using process 3 to produce integrated circuit 64, and soforth, continuing to process N, which is the newest process.

As a result of this conventional development approach, there are atleast three old versions of the circuit design of FIG. 2: integratedcircuits 60, 62, and 64. Integrated circuit 60 has a die area of 100 mm²and a delay time of 35 ns for the data pathway between data input 72 anddata output 74. Integrated circuit 60 also has test circuits and pads76. Integrated circuit 62 has a die area of 90 mm² and a delay time of24 ns for the data pathway between data input 78 and data output 80.Integrated circuit 62 also has test circuits and pads 82. Integratedcircuit 64 has a die area of 80 mm² and a delay time of 20 ns for thedata pathway between data input 84 and data output 86. Integratedcircuit 64 also has test circuits and pads 88.

Although each of integrated circuits 60, 62, and 64 may be commerciallysuccessful, users with systems designed for a given integrated circuitare generally unable to use versions of the circuit design implementedusing a new process, because the data pathway delay times in the newcircuits are too short to allow the new circuits to be interchangeablewith the old circuits. Thus, although circuits 62 and 64 are moreeconomical than circuit 60, circuits 62 and 64 are not interchangeablewith circuit 60.

In accordance with the present invention, circuits 66, 68, and 70 on theright side of FIG. 2 are fabricated using the most advanced processavailable, but with delay times arranged so that circuits 66, 68, and 70are compatible with circuits 60, 62, and 64 on the left side of FIG. 2.For example, integrated circuit 66 is fabricated using process N, so thedie area of integrated circuit 66 is 70 mm², rather than 100 mm² forintegrated circuit 60, which was fabricated using process 1. The delaytime between data input 90 and data output 92 of integrated circuit 66is 35 ns, which makes integrated circuit 66 compatible with integratedcircuit 60. Integrated circuit 66 can therefore be used interchangeablywith integrated circuit 60 in systems applications that require slowercircuits of the type of integrated circuit 60. Because integratedcircuits 60 and 66 are interchangeable, the economic benefits of usingthe smaller die area of integrated circuit 66 can be passed on to a userwho must use a circuit compatible with integrated circuit 60.

Integrated circuit 68 is fabricated using process N, so the die area ofintegrated circuit 68 is 70 mm², rather than 90 mm² for integratedcircuit 62, which was fabricated using process 2. The delay time betweendata input 94 and data output 96 of integrated circuit 68 is 24 ns,which makes integrated circuit 68 compatible with integrated circuit 62.Integrated circuit 68 can therefore be used interchangeably withintegrated circuit 62.

Integrated circuit 70 is fabricated using process N, so the die area ofintegrated circuit 70 is 70 mm², rather than 80 mm² for integratedcircuit 64, which was fabricated using process 3. The delay time betweendata input 98 and data output 100 of integrated circuit 70 is 20 ns,which makes integrated circuit 70 compatible with integrated circuit 64.If desired, integrated circuit 70 can be used interchangeably withintegrated circuit 64.

Part of the reduction in die area that is achieved when implementingintegrated circuits 60, 62, and 64 using process N is achieved byreducing the die area occupied by test circuits and pads 76, 82, and 88.The die areas occupied by test circuits and pads 102, 104, and 106 areless than the respective die areas occupied by test circuits and pads76, 82, and 88. The smaller die areas associated with test circuits andpads 102, 104, and 106 help reduce the die areas of circuits 66, 68, and70 and do not affect the delay times of the data pathways in circuits66, 68, and 70.

If desired, the die areas occupied by integrated circuits 66, 68, and 70can be further reduced by fabricating much of the remaining circuitry incircuits 66, 68, and 70 as small as possible using process N. Becausethis has the effect of reducing the delay times associated with certaincircuit components, the delay times associated with these or othercircuit components are intentionally increased to compensate, whilestill achieving an overall reduction in die area.

For example, circuit components 108, 110, and 112 of integrated circuit60 form a data pathway from data input 72 to data output 74 thatexhibits a delay time of 35 ns. Component 114 provides feedback. Inorder to reduce the die area occupied by integrated circuit 60 to 70mm², the circuitry in component 112 is reduced to the smallestdimensions possible using process N to form component 120. The circuitryin components 108, 110, and 114 is also preferably reduced in size whenforming components 116, 118, and 122, although certain structures incomponents 116, 118, and 122 are deliberately made larger than wouldotherwise be the case, so that components 116, 118, and 122 will exhibitlonger delay times. The longer delay times of components 116 and 118compensate for the reduction in the delay time associated with component120.

Specifically, reducing the dimensions of component 120 as much aspossible using process N, causes the delay time associated withcomponent 120 to drop to 6 ns compared with a delay time of 15 ns forcomponent 112. In order to compensate for this drop in delay time, thedelay times of components 116 and 118 are each increased to 14.5 ns, sothat the total delay time for integrated circuit 66 is 35 ns, asdesired. The delay time associated with feedback component 122 is alsoincreased to 14.5 ns to ensure that the operation of component 122 isproperly synchronized with components 116, 118, and 120. Because most ofthe circuitry of components 116, 118, 120, and 122 is reduced in size,the relatively small increases in the dimensions of the structures incomponents 116, 118, and 122 to adjust their delay times does not have asignificant impact on the die area of circuit 66.

Integrated circuit 68, which has a die area of 70 mm², is fabricatedsimilarly. Components 124, 126, and 128 of integrated circuit 62 form adata pathway from data input 78 to data output 80 that exhibits a delaytime of 24 ns. In order to reduce the die area occupied by integratedcircuit 62 to 70 mm², the circuitry in component 128 is reduced to thesmallest dimensions possible using process N to form component 136. Thecircuitry in components 124, 126, and 128 is also reduced in size whenforming components 132, 134, and 138, although certain structures incomponents 132, 134, and 138 are deliberately made larger than wouldotherwise be the case, so that components 132, 134, and 138 will exhibitlonger delay times.

Reducing the dimensions of component 136 as much as possible usingprocess N causes the delay associated with component 136 to drop to 6 nsfrom the delay of 10 ns associated with component 128. To compensate forthis drop in delay time, the delays of components 132 and 134 are eachincreased to 9 ns, so that the total delay for integrated circuit 68 is24 ns, as desired. The delay associated with feedback component 138 isalso increased to 9 ns, to ensure that component 138 is properlysynchronized with components 132, 134, and 136. Because most of thecircuitry of components 132, 134, 136, and 138 is reduced in size, therelatively small increases made to the dimensions of the structures incomponents 132, 134, and 138 to adjust their delay times does not have asignificant impact on the total die area of circuit 68.

The steps involved in fabricating integrated circuits such that thedelay times of new circuits are compatible with the delay times of oldcircuits are shown in FIG. 3. At step 140 an integrated circuit isfabricated using an old process (e.g., process 1). At step 142, at leastone circuit component (e.g, test circuits and pads 76 or component 112of circuit 60) is identified which is to be fabricated with reduceddimensions using the new process. The die area of the componentidentified in step 142 is reduced at step 144 while fabricating theintegrated circuit using the new process (e.g., when fabricating testcircuits and pads 102 or component 120 of circuit 66). If necessary,when fabricating a new circuit at step 146, the delay times associatedwith the circuitry of some of the components (e.g., components 116 and118 of FIG. 2) are lengthened to compensate for the shorter delayassociated with the component whose area was reduced in step 144.Preferably, the die area of more than one circuit component can bereduced and at least some of the components whose die areas are reducedcontain certain structures that are intentionally fabricated with largerdimensions to increase the delay times associated with those components.

The delay associated with a circuit component can be controlled duringfabrication by adjusting various device parameters. For example, in acomplementary metal-oxide-semiconductor (CMOS) integrated circuit, thedelay associated with a given component can be controlled by controllingthe gate lengths of some of the transistors that make up the component.Accordingly, if the integrated circuit to be fabricated in a new processwith delay times compatible with an old circuit is a CMOS device, it ispossible to adjust the delay times of various components in the datapath by controlling the lengths of the gates in the components. With theexception of the transistors whose gate lengths have been increased, thenew circuit can be fabricated with circuitry that is as small aspermitted by the new process.

For some circuit designs, maximizing the die area reduction is bestachieved when the delay times of all of the components in the datapathways of the new circuit are maintained the same as the delay timesof the corresponding components in the old circuit. This is accomplishedby reducing the dimensions of the circuitry in each of the components ofthe new circuit as much as permitted by the new process, with theexception of certain structures. The dimensions of these structures areintentionally increased, so that the delay times of the components inthe data pathway of the new circuit are maintained equal to the delaytimes of the corresponding components in the old circuit.

For other circuit designs, maximizing the die area reduction is bestachieved when the delay times of some of the components in the datapathways of the new circuit are allowed to drop relative to the delaytimes of the corresponding components in the old circuit. The delaytimes of the remaining components in the new circuit are increased tocompensate. This approach is used in the circuit design of circuits 60,62, 64, 66, 68, and 70, where the die area reduction of circuit 60 ismaximized by allowing the delay times associated with components such ascomponent 120 in circuit 66 to drop, while increasing the delay times ofthe remaining components (i.e., components 116 and 118) to compensate.

The die areas of the components whose delay times are allowed to dropare reduced considerably using the new process, whereas the die areas ofthe remaining components in the new circuit do not drop as much as theyotherwise might, because the remaining components contain certainstructures whose dimensions are increased to lengthen their associateddelay times. However, the reduction in the die areas of the componentswhose delay times drop more than offsets any adverse impact on the diearea reductions that can be achieved by the remaining components. Forcircuit designs that merit this approach, allowing some delay times togo down while others go up maximizes the net reduction in the total diearea of the new circuit.

A CMOS circuit 148 in which the die area reduction is maximized byallowing the delay time of a circuit component to drop is shown in FIG.4. CMOS circuit 148 is a programmable logic device, which is awell-known type of circuit that provides logic outputs that are aprogrammable logic function of the logic inputs to the device. Data ispassed from data input 150 to data output 152 via input buffer 154, wordline driver 156, and electrically-programmable read-only memory (EPROM)array/sense amplifier 158. A feedback circuit 160 is connected betweenthe output of EPROM array/sense amplifier 158 and the input of word linedriver 156.

Each component of circuit 148 in the data pathway between input 150 andoutput 152 has an associated delay time. Input buffer 154 has a delay of⊥₁ associated with buffer circuitry 162 and a delay of ⊥₂ associatedwith routing connections 164. Word line driver 156 has a delay of ⊥₃associated with word line driver circuitry 166 and a delay of ⊥₄associated with routing connections 168. EPROM array/sense amplifier 158has a delay of ⊥₅ associated with EPROM driver circuitry 170, a delay of⊥₆ associated with routing connections 172, and a delay of ⊥₇ associatedwith sense amplifier circuitry 174. Delays of ⊥₈ and ⊥₉ are associatedwith feedback amplifier circuitry 176 and routing connections 178 offeedback circuit 160, respectively.

Test circuits and pads 180 are also part of circuit 148, but do notaffect the data pathway between input 150 and output 152.

Because circuit 148 is a CMOS circuit, the delay time associated witheach logic component can be controlled by varying the gate lengths ofthe transistors in the component. CMOS circuits are made up of n-channeland p-channel field-effect transistors. In order to avoiddrain-to-source breakdown under high voltage conditions, p-channel gatelengths sometimes must be slightly larger than the gate lengths ofcomparable n-channel transistors. Preferably, the gate lengths to bevaried to adjust the delay times with a given circuit design areparameterized. As shown in FIG. 4, parameters P₁ and P₂ are associatedwith buffer circuitry 162. P₁ is a parameter representing the gatelengths of n-channel transistors in buffer circuitry 162. P₂ is aparameter representing the gate lengths of p-channel transistors inbuffer circuitry 162. Parameters P₁ and P₂ are also associated with wordline driver circuitry 166. Parameters P₃ and P₄, which represent thegate length of n- and p-channel transistors, respectively, areassociated with feedback amplifier circuitry 176.

The attributes of four different circuit implementations (Nos. 1-4)using the circuit design of circuit 148 are set forth in the table ofFIG. 5. The process used for each circuit and the minimum gate lengthsthat can be achieved using that process are listed. The parameters P₁,P₂, P₃, and P₄ define the gate lengths of the transistors in buffercircuitry 162, word line driver circuitry 166, and feedback amplifiercircuitry 176. For each circuit, the delays ⊥₁ -⊥₉ associated with thatcircuit and the total delay time associated with the data pathway frominput 150 to output 152 are given.

Circuit Nos. 1 and 3 are older circuits, implemented using processes 1and 2, respectively. Circuit Nos. 2 and 4 are fabricated using processN, which is a newer, more advanced process than processes 1 and 2.Circuit No. 2 is compatible with circuit No. 1, but occupies less diearea than circuit No. 1. Circuit No. 4 is compatible with circuit No. 3,but occupies less die area than circuit No. 3.

The smallest lateral dimension and thus minimum gate length that can befabricated using process 1 is 1.5 μm. As shown in the table in FIG. 5,gate lengths of 1.5 μm are used in circuit No. 1 for the transistors inbuffer circuitry 162, word line driver circuitry 166, and feedbackamplifier circuitry 176. The remaining circuitry in circuit No. 1, suchas the circuitry in EPROM array/sense amplifier 158, is fabricated assmall as permitted by process 1 (i.e., with lateral dimensions of 1.5μm). The delay times ⊥₁ -⊥₉ for circuit No. 1 result in a total delaytime of 35 ns for data passing from input 150 to output 152.

When the circuit design of circuit No. 1 is implemented using process N,it becomes possible to shrink the circuit die area. With process N, theminimum lateral dimension that can be fabricated is 0.65 μm. Circuit No.2 uses the same circuit design as circuit No. 1, but is fabricated usingprocess N. Certain components in circuit No. 2 are fabricated as smallas permitted by process N.

For example, EPROM array/sense amplifier 158 of circuit No. 2 isfabricated with lateral dimensions of 0.65 μm, which reduces the diearea occupied by EPROM array/sense amplifier 158 in circuit No. 2relative to that of circuit No. 1. Fabricating EPROM array/senseamplifier 158 with lateral dimensions of 0.65 μm also has the effect ofreducing the delay times associated with EPROM array/sense amplifier 158(⊥₅ -⊥₇) by a total of 9 ns. All of the circuit dimensions in EPROMarray/sense amplifier 158 are shrunk to the minimum allowed by processN, because EPROM array/sense amplifier 158 occupies a fairly largefraction (about 10%) of the total die area of circuit 148 and becauseincreasing the gate lengths of the transistors in EPROM array/senseamplifier 158 even a small amount has a relatively large impact on thetotal area occupied by EPROM array/sense amplifier 158. Allowing thedelay time associated with EPROM array/sense amplifier 158 to decreaseso that EPROM array/sense amplifier 158 can be reduced considerably indie area helps to maximize the die area reduction of circuit No. 2.

Test circuits and pads 180 are also fabricated at 0.65 μm in circuit No.2, which reduces the die area associated with this portion of thecircuit. Portions of input buffer circuitry 162, word line drivercircuitry 166, and feedback amplifier circuitry 176 are fabricated assmall as permitted by process N (0.65 μm), but the gate lengths of atleast some selected transistors in input buffer circuitry 162, word linedriver circuitry 166, and feedback amplifier circuitry 176 arefabricated with intentionally larger gate lengths to increase the delaytimes associated with these components sufficiently to compensate forthe 9 ns decrease in the total delay time due to the faster operation ofEPROM array/sense amplifier 158.

As indicated in the table of FIG. 5, in circuit No. 2 both n- andp-channel transistors in input buffer circuitry 162 and word line drivercircuitry 166 are fabricated with gate lengths of 3.0 μm. Feedbackamplifier circuitry 176 is fabricated with gate lengths of 3.7 μm. Theincreased gate lengths dictated by these values of parameters P₁ -P₄cause the delay times associated with input buffer circuitry 162, wordline driver circuitry 166, and feedback amplifier circuitry 176 (⊥₁, ⊥₃,and ⊥₈) to increase from 5 ns to 9.5 ns each. As a result, the totaldelay time of the data pathway between input 150 to output 152 increasesby 9 ns, compensating for the 9 ns decrease in the total delay time dueto the faster operation of EPROM array/sense amplifier 158. The totaldelay time of circuit No. 2 is therefore 35 ns, which is the same as thetotal delay time of circuit No. 1. Because the total delay times ofcircuit Nos. 1 and 2 are equal, circuit Nos. 1 and 2 can be usedinterchangeably.

The smallest lateral dimension and minimum gate length that can befabricated using process 2 is 1.0 μm. As shown in the table of FIG. 5,gate lengths of 1.0 μm are used in circuit No. 3 for the transistors inbuffer circuitry 162, word line driver circuitry 166, and feedbackamplifier circuitry 176. The remaining circuitry in circuit No. 3, suchas the circuitry in EPROM array/sense amplifier 158, is fabricated assmall as permitted by process 2 (i.e., with lateral dimensions of 1.0μm). The delay times ⊥₁ -⊥₉ for circuit No. 3 result in a total delaytime of 24 ns for data passing from input 150 to output 152.

When the circuit design of circuit No. 3 is implemented using process N,it becomes possible to shrink the circuit die area. With process N, theminimum lateral dimension that can be fabricated is 0.65 μm. Circuit No.4 uses the same circuit design as circuit No. 3, but is fabricated usingprocess N. Certain components in circuit No. 4 are fabricated as smallas permitted by process N. For example, EPROM array/sense amplifier 158of circuit No. 4 is fabricated with lateral dimensions of 0.65 μm, whichreduces the die area occupied by EPROM array/sense amplifier 158 incircuit No. 4 relative to that of circuit No. 3. Fabricating EPROMarray/sense amplifier 158 with lateral dimensions of 0.65 μm also hasthe effect of reducing the delay times in circuit No. 4 associated withEPROM array/sense amplifier 158 (⊥₅ -⊥₇) by a total of 4 ns.

Test circuits and pads 180 in circuit No. 4 are also fabricated at 0.65μm, which reduces the die area associated with that portion of thecircuit. Portions of input buffer circuitry 162, word line drivercircuitry 166, and feedback amplifier circuitry 176 are fabricated assmall as permitted by process N (0.65 μm), but the gate lengths of atleast some selected transistors in input buffer circuitry 162, word linedriver circuitry 166, and feedback amplifier circuitry 176 arefabricated with intentionally larger gate lengths to increase the delaytimes associated with these components sufficiently to compensate forthe 4 ns decrease in the total delay time due to the faster operation ofEPROM array/sense amplifier 158.

As indicated in the table of FIG. 5, in circuit No. 4 both n- andp-channel transistors in input buffer circuitry 162, word line drivercircuitry 166, and feedback amplifier circuitry 176 are fabricated withgate lengths of 1.5 μm. The increased gate lengths dictated by thesevalues of parameters P₁ -P₄ cause the delay times associated with inputbuffer circuitry 162, word line driver circuitry 166, and feedbackamplifier circuitry 176 (⊥₁, ⊥₃, and ⊥₈) to increase from 3 ns to 5 nseach. As a result, the total delay time of the data pathway betweeninput 150 to output 152 increases by 4 ns, which compensates for the 4ns decrease in the total delay time due to the faster operation of EPROMarray/sense amplifier 158. The total delay time of circuit No. 4 istherefore 24 ns, which is the same as the total delay time of circuitNo. 3. Because the total delay times of circuit Nos. 3 and 4 are equal,circuit Nos. 3 and 4 can be used interchangeably.

One of the advantages of the present invention is that a circuitoriginally implemented using an old process can be implemented using anew process and yet have delay times for the data pathways through thenew circuit that are compatible with the old circuit. Such new circuitsare interchangeable with old circuits, but are more economical tomanufacture and have lower power consumptions due to their reduced dieareas. Another advantage of the present invention is that a commoncircuit layout can be developed for use with the new process. The commonlayout can then be used to fabricate a family of new circuits, each ofwhich is interchangeable with a corresponding one of a number of oldcircuits.

For example, as shown in FIG. 6, when a circuit design is implementedusing a number of different processes over a period of time, a group ofold circuits 182, 184, and 186 is developed. Circuits 182, 184, and 186share a common circuit design, but because each circuit is implementedusing a different process, each circuit has different delay timesassociated with its data pathways. In order to replace old circuits 182,184, and 186 with compatible new circuits, a common circuit layout 188is created for use with process N.

Process N is a new, more advanced process than processes 1, 2, and 3.New circuits 190, 192, and 194 are fabricated using process N andtherefore have smaller die areas and lower power consumptions thanrespective old circuits 182, 184, and 186.

The entire family of new circuits 190, 192, and 194 is fabricated usinga common circuit layout 188. The only physical difference betweencircuits 190, 192, and 194 is that certain structures (such as the gatesof some of the transistors) are fabricated with dimensions governed byadjustable parameters. The dimensions of these structures govern theassociated delay times of the logic components in which they arecontained.

In FIG. 6, parameter P corresponds to the gate length of certaintransistors in the circuits 190, 192, and 194. In circuit 190, the valueof P is 5 μm, which makes new circuit 190 interchangeable with oldcircuit 182 by ensuring that the total data pathway delay time for newcircuit 190 is equal to the total data pathway delay time for oldcircuit 182. In circuit 192, the value of P is 3.5 μm, which makes newcircuit 192 interchangeable with old circuit 184 by ensuring that thetotal data pathway delay time for new circuit 192 is equal to the totaldata pathway delay time for old circuit 184. In circuit 194, the valueof P is 2.5 μm, which makes new circuit 194 interchangeable with oldcircuit 186 by ensuring that the total data pathway delay time for newcircuit 194 is equal to the total data pathway delay time for oldcircuit 186. Only a single parameter (P) is used in conjunction withcommon layout 188, but numerous parameters (e.g., P₁ /P₂ and P₃ /P₄ ofcircuit 148 in FIG. 4) can be used, if desired.

As with any integrated circuit design, a number of masks are used tofabricate a complete circuit. Using a common layout allows the majorityof these masks to be the same for each circuit in the family of newcircuits. Only a few masks (e.g., the gate level masks) must becustomized for circuits 190, 192, and 194, to allow the structures (suchas the gates) that have sizes determined by the adjustable parameter Pto be fabricated appropriately for each circuit.

The steps involved in fabricating a family of new circuits using acommon layout are shown in FIG. 7. At step 196, a suitable common layoutis created from which a family of new circuits can be constructed. Atleast one structure in the common layout has dimensions which aregoverned by a variable parameter. The dimensions of the structuredetermine the delay time associated with the logic component in whichthe structure is contained. At step 198, a family of parameter values isgenerated. Each parameter value is associated with a new circuit. Atstep 200, the family of new circuits is fabricated. Each new circuit inthe family is fabricated based on the parameter values associated withthat circuit using the common layout created at step 196. The totaldelay time of each new circuit is equal to the total delay time of thecorresponding old circuit.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention.

What is claimed is:
 1. A method of fabricating integrated circuits inwhich a circuit design originally implemented using an old process toform a first integrated circuit is implemented using a new fabricationprocess to form a second integrated circuit, said second integratedcircuit having a die area that is smaller than that of said firstintegrated circuit, said first and second integrated circuits eachhaving a data input, a data output, and a plurality of components eachoccupying a respective die area, at least some of said components havingan associated delay time and being connected between said data input andsaid data output to form a pathway having a total delay time, saidmethod comprising the steps of:identifying a predetermined component onsaid first integrated circuit with a die area that can be reduced byfabricating said predetermined component with said new fabricationprocess; and fabricating said second integrated circuit including saidpredetermined component using said new fabrication process on saidsecond integrated circuit, said predetermined component having a diearea that is reduced relative to said die area of said predeterminedcomponent on said first integrated circuit, said total delay time ofsaid pathway on said second integrated circuit being equal to said totaldelay time of said pathway on said first integrated circuit.
 2. Themethod defined in claim 1 wherein said predetermined component on saidfirst integrated circuit with a die area that can be reduced is testcircuits and pads, said step of fabricating said predetermined componentusing said new fabrication process comprising the step of fabricatingsaid test circuits and pads on said second integrated circuit with a diearea that is reduced relative to said die area of said test circuits andpads on said first integrated circuit.
 3. The method defined in claim 1wherein said predetermined component is one of the components in saidpathway between said data input and said data output having one of saidassociated delay times, said step of fabricating said predeterminedcomponent comprising the step of fabricating said predeterminedcomponent using said new fabrication process on said second integratedcircuit with an associated delay time that is reduced relative to saidassociated delay time of said predetermined component on said firstintegrated circuit, said method further comprising the step offabricating at least one of said components in said pathway other thansaid predetermined component using said new fabrication process on saidsecond integrated circuit with an associated delay time that isincreased to compensate for the reduced associated delay time of saidpredetermined component.
 4. The method defined in claim 3 wherein saidpredetermined component is EPROM array/sense amplifier circuitry, saidEPROM array/sense amplifier circuitry having a die area and anassociated delay time on said first integrated circuit, said step offabricating said predetermined component comprising the step offabricating said EPROM array/sense amplifier circuitry using said newprocess on said second integrated circuit with a die area that isreduced relative to said die area of said EPROM array/sense amplifiercircuitry on said first integrated circuit and with a reduced associateddelay time relative to said associated delay time of said EPROMarray/sense amplifier on said first integrated circuit.
 5. The methoddefined in claim 4 wherein said at least one component in said pathwayother than said predetermined component includes input buffer circuitryand word line driver circuitry, each having a die area and an associateddelay time on said first integrated circuit, said step of fabricatingsaid at least one component in said pathway other than saidpredetermined component comprising the step of fabricating said inputbuffer circuitry and said word line driver circuitry using said newfabrication process on said second integrated circuit such that saidassociated delay times of said input buffer circuitry and said word linedriver circuitry are increased to compensate for said reduced associateddelay time of said EPROM array/sense amplifier circuitry.
 6. The methoddefined in claim 5 wherein said first and second integrated circuitseach further comprise feedback circuitry having an associated delaytime, said feedback circuitry connecting said EPROM array/senseamplifier circuitry to said word line driver circuitry, said methodfurther comprising the step of fabricating said feedback circuitry onsaid second integrated circuit with said new fabrication process, saidassociated delay time of said feedback circuitry on said secondintegrated circuit being increased relative to said associated delaytime of said feedback circuitry on said first integrated circuit so thatsaid feedback circuitry is synchronized with said EPROM array/senseamplifier circuitry and said word line driver circuitry.
 7. A method offabricating integrated circuits in which a circuit design originallyimplemented using a plurality of old fabrication processes to form aplurality of old circuits is implemented using a new fabrication processto form a family of new circuits, said new fabrication process allowingsaid new circuits to be fabricated with smaller die areas than said oldcircuits, each new circuit being interchangeable with a correspondingone of said old circuits and having a smaller die area than saidcorresponding one of said old circuits, said old circuits and said newcircuits each having a data input, a data output, and a plurality ofcomponents, said components having associated delay times and beingconnected between said data input and said data output to form a pathwayhaving a total delay time, said method comprising the steps of:creatinga common layout from which said family of new circuits can beconstructed and which has a component containing a structure that has anassociated parameter; generating a family of parameter values for saidparameter, such that for each new circuit one of said parameter valuesgoverns the dimensions of said structure in said component, saiddimensions governing said associated delay time of said component; andfabricating said family of new circuits using said new process, saidtotal delay time of each new circuit being equal to said total delaytime of said corresponding old circuit.